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Патенты сотрудников кафедры и лаборатории

  1. Chen Jian-Guo, Mazurenko I.L., Meng-Lin Yu, Petyushko A.A. Preamble detection using vector processors US Patent 9184787. November 10, 2015. www.google.com/patents/US9184787
  2. Бабин Д.Н., Мазуренко И.Л., Холоденко А.Б., Пархоменко Д.В., Михайлов Д.С., Уранцев А.В. Способ определения текущего состояния глаз оператора при контроле бодрствования.
    Патент РФ 2563091, 20.09.2015. 2563091.pdf
  3. Aliseychik P.A., Evers Petrus Sebastiaan Adrianus Daniel, Parfenov D.V., Filippov A.N., Zaytsev D.V. Program module applicability analyzer for software development and testing for multi-processor environments. United States Patent: 9,043,770, May 26, 2015. http://patft.uspto.gov/[...]
  4. Petyushko A.A., Bolotov A.A., Han Yang, Mazurenko I.L., Kholodenko A.B., Zaytsev D.V., Parfenov D.V. Method for selecting a LDPC candidate code. United States Patent: 9,037,944, May 19, 2015. http://patft.uspto.gov/[...]
  5. Zaytsev D.V., Parfenov D.V., Han Yang, Mazurenko I.L., Babin D.N. Efficient way to construct LDPC code by comparing error events using a voting based method. United States Patent: 8,977,925, March 10, 2015. http://patft.uspto.gov/[...]
  6. Sokolov A.P., Gasanov E.E., Neznanov I.V., Aliseychik P.A., Panteleev P.A. Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards. United States Patent: 8,938,654, January 20, 2015. http://patft.uspto.gov/[...]
  7. Babin D.N., Parkhomenko D.V., Mazurenko I.L., Parfenov D.V., Filippov A.N. Double precision approximation of a single precision operation. United States Patent: 8,924,447, December 30, 2014. http://patft.uspto.gov/[...]
  8. Shutkin Yu.S., Neznanov I. V., Sokolov A. P., Panteleev P. A., Gasanov E. E. Optimization of data processors with irregular patterns. United States Patent: 8,923,413, December 30, 2014. http://patft.uspto.gov/[...]
  9. Aliseychik P.A., Gasanov E. E., Neznanov I. V., Panteleev P. A., Sokolov A. P. Packet router having a hierarchical buffer structure. United States Patent: 8,923,315, December 30, 2014. http://patft.uspto.gov/[...]
  10. Irmatov A.A., Buryak D.Yu., Cherdakov D.V., Lee D.S. Face detection method and apparatus. United States Patent: 8,885,943, November 11, 2014. http://patft.uspto.gov/[...]
  11. Shutkin Yu.S., Gasanov E. E., Neznanov I. V., Sokolov A. P., Panteleev P. A. No-delay microsequencer. United States Patent: 8,868,890, October 21, 2014. http://patft.uspto.gov/[...]
  12. Shutkin Yu.S., Aliseychik P.A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Panteleev P. A. Two-pass linear complexity task scheduler. United States Patent: 8,850,437, September 30, 2014. http://patft.uspto.gov/[...]
  13. Sokolov A. P., Panteleev P. A., Gasanov E. E., Neznanov I. V., Shutkin Yu.S. L-value generation in a decoder. United States Patent: 8,842,784, September 23, 2014. http://patft.uspto.gov/[...]
  14. Bolotov A.A., Letunovskiy A.A., Mazurenko I.L., Ivanovic L.D., Zhang Fan. Dynamically controlling the number of local iterations in an iterative decoder. United States Patent: 8,832,532, September 9, 2014. http://patft.uspto.gov/[...]
  15. Mazurenko I. L.Babin D.N., Parfenov D.V., Petyushko A. A., Markovic A. Time-domain acoustic echo control. United States Patent: 8,824,667, September 2, 2014. http://patft.uspto.gov/[...]
  16. Petyushko A. A., Babin D.N., Shaw D.G., Mazurenko I. L.Aliseychik P.A. Fast echo gain change detection. United States Patent: 8,817,970, August 26, 2014. http://patft.uspto.gov/[...]
  17. Mazurenko I. L.Babin D.N., Parkhomenko D.V., Petyushko A. A., Parfenov D.V. Stochastic vector based network echo cancellation. United States Patent: 8,804,946, August 12, 2014. http://patft.uspto.gov/[...]
  18. Mazurenko I.L., Petyushko A.A., Meng-Lin Yu, Chen Jian-Guo. Chunk-based double-dwell preamble detection. United States Patent: 8,804,672, August 12, 2014. http://patft.uspto.gov/[...]
  19. Mazurenko I. L., Letunovskiy A.A., Markovic A., Parfenov D.V., Petyushko A. A. Intra-mode prediction for a video transcoder. United States Patent: 8,780,983, July 15, 2014. http://patft.uspto.gov/[...]
  20. Gasanov E. E., Panteleev P. A., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Radix-4 viterbi forward error correction decoding. United States Patent: 8,775,914, July 8, 2014. http://patft.uspto.gov/[...]
  21. Panteleev P. A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Variable parity encoder. United States Patent: 8,775,893, July 8, 2014. http://patft.uspto.gov/[...]
  22. Letunovskiy A.A., Lyalin I.V., Markovic A., Mazurenko I.L., Nikitin A.A. High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs). United States Patent: 8,761,916, June 24, 2014. http://patft.uspto.gov/[...]
  23. Parfenov D.V., Aliseychik P.A., Letunovskiy A.A., Markovic A., Mazurenko I.L., Parkhomenko D.V. Video transcoder with flexible quality and complexity management. United States Patent: 8,731,068, May 20, 2014. http://patft.uspto.gov/[...]
  24. Aliseychik P.A., Letunovskiy A.A., Petyushko A. A., Parkhomenko D.V., Kholodenko A.B. Accelerator for a read-channel design and simulation tool. United States Patent: 8,713,495. April 29, 2014. http://patft.uspto.gov/[...]
  25. Letunovskiy Aleksey, Parfenov Denis, Mazurenko Ivan, Markovic Alexander, Petyushko Alexander. Motion estimation for a video transcoder. United States Patent: 8,711,941, April 29, 2014. http://patft.uspto.gov/[...]
  26. Panteleev P. A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Reconfigurable encoding per multiple communications standards. United States Patent: 8,700,969, April 15, 2014. http://patft.uspto.gov/[...]
  27. Panteleev P. A., Gasanov E. E., Neznanov I. V., Sokolov A. P., Shutkin Yu.S. Branch metrics calculation for multiple communications standards. United States Patent: 8,699,396. April 15, 2014. http://patft.uspto.gov/[...]
  28. Irmatov A.A., Buryak D.Yu., Kuznetsov V.D., Cherdakov D. V., Yang H.-K., Lee D.S. Method and apparatus for recognizing a protrusion on a face. United States Patent: 8,698,914, April 15, 2014. http://patft.uspto.gov/[...]
  29. Gasanov E.E., Neznanov I.V., Shutkin Yu.S., Sokolov A.P., Panteleev P.A. Timer manager architecture based on binary heap. United States Patent: 8,656,206, February 18, 2014. https://patents.google.com/patent/US8656206B2/
  30. Panteleev P.A., Gasanov E.E., Neznanov I.V., Sokolov A.P., Shutkin Yu.A. Reconfigurable BCH decoder. United States Patent: 8,621,329, December 31, 2013. http://patft.uspto.gov/[...]
  31. Andreev A.E., Nikitin A.A., Scepanovic R., Vikhliantsev I.A. Method and apparatus for generating memory models and timing database. United States Patent: 8,566,769, October 22, 2013. http://patft.uspto.gov/[...]
  32. Aliseychik P.A., Gasanov E.E., Izyumin O.N., Neznanov I.V., Panteleev P.A. Parallel true random number generator architecture. United States Patent: 8,539,009, September 17, 2013. http://patft.uspto.gov/[...]
  33. Andreev A.E., Gasanov E.E., Aliseychik P.A., Neznanov I.V., Panteleev P.A. System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors. United States Patent: 8,527,851, September 3, 2013. http://patft.uspto.gov/[...]
  34. Nikitin A.A, Scepanovic R., Kucherenko I.V., Lau W., Kong Cheng-Gang, Seto Hui-Yin, Zolotykh A.A., Pavisic I., Bhutani S., Lu A., Lyalin I.V.. Method and computer program for generating grounded shielding wires for signal wiring. United States Patent: 8,516,425, August 20, 2013. http://patft.uspto.gov/[...]
  35. Mazurenko I.L., Aleshin S.V., Lyalin I.V., Nikitin A.A., Parfenov D.V. Adaptive filtering with flexible selection of algorithm complexity and performance. United States Patent: 8,515,055, August 20, 2013. http://patft.uspto.gov/[...]
  36. Alekseev D.V., Galatenko A.V., Letunovskiy A.A., Markovic A., Nikitin A.A. Cryptographic processing using a processor. United States Patent: 8,452,006, May 28, 2013. http://patft.uspto.gov/[...]
  37. Alekseev D.V., Galatenko A.V., Lyalin I.V., Markovic A., Parfenov D.V. Hash processing using a processor. United States Patent: 8,447,988, May 21, 2013. http://patft.uspto.gov/[...]
  38. Andreev A.E., Gribok S.Y., Izyumin O. Variable node processing unit. United States Patent: 8,443,033, May 14, 2013. http://patft.uspto.gov/[...]
  39. Irmatov A.A., Belousov A., Cadouri E., Gratchev A., Ryjov A.P., Thenie L. Method and mechanism for extraction and recognition of polygons in an IC design. United States Patent: 8,429,588, April 23, 2013. http://patft.uspto.gov/[...]
  40. Neznanov I.V., Gasanov E.E., Panteleev P.A., Aliseychik P.A., Sokolov A.P. BCH or reed-solomon decoder with syndrome modification. United States Patent: 8,397,143, March 12, 2013. http://patft.uspto.gov/[...]
  41. Gasanov E.E., Sokolov A.P., Panteleev P.A., Neznanov I.V., Aliseychik P.A. Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder. United States Patent: 8,365,054, January 29, 2013. http://patft.uspto.gov/[...]
  42. Andreev A.E., Vukovic V., Vikhliantsev I.A. Circuits for implementing parity computation in a parallel architecture LDPC decoder. United States Patent: 8,347,167, January 1, 2013. http://patft.uspto.gov/[...]
  43. Gashkov S.B., Andreev A.E. Universal Galois field multiplier. United States Patent: 8,312,072, November 13, 2012. http://patft.uspto.gov/[...]
  44. Bolotov A.A., Grinchuk M.I., Ivanovic L.D., Galatenko A.V. Architecture and implementation method of programmable arithmetic controller for cryptographic applications. United States Patent: 8,302,083, October 30, 2012. http://patft.uspto.gov/[...]
  45. Panteleev P.A., Gasanov E.E., Andreev A.E., Neznanov I.V., Aliseychik P.A. Scheme for erasure locator polynomial calculation in error-and-erasure decoder. United States Patent: 8,286,060, October 9, 2012. http://patft.uspto.gov/[...]
  46. Gribok S.Y., Andreev A.E., Gashkov S.B. Cryptographic random number generator using finite field operations. United States Patent: 8,250,129, August 21, 2012. http://patft.uspto.gov/[...]
  47. Andreev A.E., Nikitin А.A., Scepanovic R., Vikhliantsev I.A. Method and apparatus for generating memory models and timing database. United States Patent: 8,245,168, August 14, 2012. http://patft.uspto.gov/[...]
  48. Nikitin Andrey, Scepanovic Ranko, Kucherenko Igor, Lau William, Kong Cheng-Gang, Seto Hui-Yin, Zolotykh Andrej, Pavisic Ivan, Bhutani Sandeep, Lu Aiguo, Lyalin Ilya. Method and apparatus for balancing signal delay skew. United States Patent: 8,239,813, August 7, 2012. http://patft.uspto.gov/[...]
  49. Andreev A.E., Neznanov I.V., Gasanov E.E., Panteleev P.A. Reed-solomon decoder with a variable number of correctable errors. United States Patent: 8,209,589, June 26, 2012. http://patft.uspto.gov/[...]
  50. Andreev A.E., Neznanov I.V., Gasanov E.E., Panteleev P.A. Configurable Reed-Solomon decoder based on modified Forney. United States Patent: 8,181,096, May 15, 2012. http://patft.uspto.gov/[...]
  51. Panteleev P.A., Andreev A.E., Gasanov E.E., Neznanov I.V. Variable redundancy reed-solomon encoder. United States Patent: 8,176,397, May 8, 2012. http://patft.uspto.gov/[...]
  52. Grinchuk M.I., Bolotov A.A., Ivanovic L.D., Zolotykh A.A., Galatenko A.V. Efficient implementation of arithmetical secure hash techniques. United States Patent: 8,160,242, April 17, 2012. http://patft.uspto.gov/[...]
  53. Andreev A.E., Bolotov A.A., Grinchuk M.I. Data controlling in the MBIST chain architecture. United States Patent: 8,156,391, April 10, 2012. http://patft.uspto.gov/[...]
  54. Andreev A.E., Vikhliantsev I.A. Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same. United States Patent: 8,151,160, April 3, 2012. http://patft.uspto.gov/[...]
  55. Andreev A.E., Bolotov A.A., Scepanovic R. Memory mapping for parallel turbo decoding. United States Patent: 8,132,075, March 6, 2012. http://patft.uspto.gov/[...]
  56. Andreev A.E., Gribok S.Y., Vukovic V. System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units. United States Patent: 8,095,845, January 10, 2012. http://patft.uspto.gov/[...]
  57. Andreev A.E., Bolotov A.A., Grinchuk M.I. Transport subsystem for an MBIST chain architecture. United States Patent: 8,046,643. October 25, 2011. http://patft.uspto.gov/[...]
  58. Andreev A.E., Nikitin А.A., Neznanov I.V., Scepanovic R. Method and apparatus for mapping design memories to integrated circuit layout. United States Patent: 8,037,432. October 11, 2011. http://patft.uspto.gov/[...]
  59. Andreev A.E., Gribok S.Y., Izyumin O., Scepanovic R., Vikhliantsev I.A., Vukovic V. Methods and apparatus for programmable decoding of a plurality of code types. United States Patent: 8,035,537. October 11, 2011. http://patft.uspto.gov/[...]
  60. Ирматов А.А., Буряк Д.Ю., Чердаков Д.В., Кузнецов В.Д., Янг Х.Е., Ли Д.С. Способ и устройство распознавания рельефности лица. Патент РФ № 2431190, 10 октября, 2011. http://www.findpatent.ru/patent/243/2431190.html
  61. Ирматов А.А., Буряк Д.Ю., Чердаков Д.В., Ли Д.С. Способ и устройство обнаружения лиц на изображении с применением каскада классификаторов. Патент РФ № 2427911, 27 августа 2011. http://www.findpatent.ru/patent/242/2427911.html
  62. Nikitin А.A., Andreev A.E., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 8,006,209, August 23, 2011. http://patft.uspto.gov/[...]
  63. Andreev A.E., Bolotov A.A., Grinchuk M.I. Address controlling in the MBIST chain architecture. United States Patent: 7,949,909, May 24, 2011. http://patft.uspto.gov/[...]
  64. Andreev A.E., Vikhliantsev I.A., Gribok S. Parallel LDPC decoder. United States Patent: 7,934,139, April 26, 2011. http://patft.uspto.gov/[...]
  65. Gribok S., Andreev A.E., Vikhliantsev I.A. Low complexity LDPC encoding algorithm. United States Patent: 7,913,149, March 22, 2011. http://patft.uspto.gov/[...]
  66. Irmatov A.A., Belousov A., Cadouri E., Gratchev A., Ryjov A.P., Thenie L. Method and mechanism for extraction and recognition of polygons in an IC design. United States Patent: 7,908,579, March 15, 2011. http://patft.uspto.gov/[...]
  67. Andreev A.E., Bolotov A.A. Built in test controller with a downloadable testing program. United States Patent: 7,882,406, February 1, 2011. http://patft.uspto.gov/[...]
  68. Andreev A.E., Vukovic V., Scepanovic R. Decision tree representation of a function. United States Patent: 7,877,724, January 25, 2011. http://patft.uspto.gov/[...]
  69. Andreev A.E., Bolotov A.A., Scepanovic R. Command language for memory testing. United States Patent: 7,856,577, December 21, 2010. http://patft.uspto.gov/[...]
  70. Ирматов А.А., Белоусов А., Кадоури Э., Грачев А., Рыжов А.П., Тени Л. Метод и механизм экстракции и распознавания многоугольников при проектировании интегральных схем. Патент РФ № 2406136, 10 декабря, 2010. http://www.findpatent.ru/patent/240/2406136.html
  71. Gasanov E.E., Andreev A.E., Neznanov I.V., Panteleev P.A., Gashkov S.B. Low area architecture in BCH decoder. United States Patent: 7,823,050, October 26, 2010. http://patft.uspto.gov/[...]
  72. Nikitin А.A., Andreev A.E., Vikhliantsev I.A. Digital Gaussian noise simulator. United States Patent: 7,822,099, October 26, 2010. http://patft.uspto.gov/[...]
  73. Andreev A.E., Pavisic I., Bolotov A.A. Density driven layout for RRAM configuration module. United States Patent: 7,818,703, October 19, 2010. http://patft.uspto.gov/[...]
  74. Andreev A.E., Bolotov A.A., Scepanovic R. Generation of test sequences during memory built-in self testing of multiple memories. United States Patent: 7,788,563, August 31, 2010. http://patft.uspto.gov/[...]
  75. Andreev A.E., Vukovic V., Scepanovic R. Pipelined LDPC arithmetic unit. United States Patent: 7,739,575, June 15, 2010. http://patft.uspto.gov/[...]
  76. Andreev A.E., Vikhliantsev I.A., Scepanovic R. High performance tiling for RRAM memory. United States Patent: 7,739,471, June 15, 2010. http://patft.uspto.gov/[...]
  77. Andreev A.E., Pavisic I., Vikhliantsev I.A. Methods and apparatus for fast unbalanced pipeline architecture. United States Patent: 7,667,494, February 23, 2010. http://patft.uspto.gov/[...]
  78. Ирматов А.А., Кузнецов В.Д., Буряк Д.Ю., Чердаков Д.В., Ли Д.С., Мун В.Ж., Ли Я.Ж. Способ и система для обнаружения лица. Патент РФ № 2382407, 20 февраля 2010. http://www.findpatent.ru/patent/238/2382407.html
  79. Ирматов А.А., Буряк Д.Ю., Чердаков Д.В., Кузнецов В.Д., Мун В.Ж., Ли Я.Ж., Янг Х.Е., Ли Д.С. Способ и система для распознавания лица с учетом списка людей, не подлежащих проверке. Патент РФ № 2381553, 10 февраля 2010. http://www.findpatent.ru/patent/238/2381553.html
  80. Andreev A.E. Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data. United States Patent: 7,656,325, February 2, 2010. http://patft.uspto.gov/[...]
  81. Andreev A.E., Nikitin А.A., Scepanovic R., Vikhliantsev I.A. Method and apparatus for generating memory models and timing database. United States Patent: 7,584,442, September 1, 2009. http://patft.uspto.gov/[...]
  82. Zolotykh A.A., Gasanov E.E., Galatenko A.V., Lyalin I.V. Ramptime propagation on designs with cycles. United States Patent: 7,568,175, July 28, 2009. http://patft.uspto.gov/[...]
  83. Andreev A.E., Bolotov A.A. Sequential tester for longest prefix search engines. United States Patent: 7,548,844, June 16, 2009. http://patft.uspto.gov/[...]
  84. Gribok S.V., Andreev A.E., Pavisic I. Built in self test transport controller architecture. United States Patent: 7,546,505, June 9, 2009. http://patft.uspto.gov/[...]
  85. Andreev A.E., Nikitin A.A., Scepanovic R. Multimode delay analysis for simplifying integrated circuit design timing models. United States Patent: 7,512,918, March 31, 2009. http://patft.uspto.gov/[...]
  86. Lyalin I.V., Zolotykh A.A., Gasanov E.E., Galatenko A.V. Method of selecting cells in logic restructuring. United States Patent: 7,496,870, February 24, 2009. http://patft.uspto.gov/[...]
  87. Rodin S.B., Aleshin S.V., Golubtsov I. Automatic recognition of geometric points in a target IC design for OPC mask quality calculation. United States Patent: 7,493,577, February 17, 2009. http://patft.uspto.gov/[...]
  88. Andreev A.E., Vukovic V., Gribok S.V. RRAM memory error emulation. United States Patent: 7,493,519, February 17, 2009. http://patft.uspto.gov/[...]
  89. Nikitin A.A., Andreev A.E., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 7,472,358, December 30, 2008. http://patft.uspto.gov/[...]
  90. Andreev A.E., Gribok S.V., Bolotov A.A. Memory BISR architecture for a slice. United States Patent: 7,430,694, September 30, 2008. http://patft.uspto.gov/[...]
  91. Andreev A.E., Nikitin A.A., Neznanov I.V., Scepanovic R. Method and apparatus for mapping design memories to integrated circuit layout. United States Patent: 7,424,687, September 9, 2008. http://patft.uspto.gov/[...]
  92. Andreev A.E., Nikitin A.A., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 7,415,691, August 19, 2008. http://patft.uspto.gov/[...]
  93. Andreev A.E., Bolotov A.A., Scepanovic R. Memory timing model with back-annotating. United States Patent: 7,415,686, August 19, 2008. http://patft.uspto.gov/[...]
  94. Uzhakov S.V., Aleshin S.V., Medvedeva M.M. Method and system for improving aerial image simulation speeds. United States Patent: 7,406,675, July 29, 2008. http://patft.uspto.gov/[...]
  95. Andreev A.E., Panteleev P.A., Nikitin A.A. Method and system for mapping netlist of integrated circuit to design. United States Patent: 7,404,166, July 22, 2008. http://patft.uspto.gov/[...]
  96. Aleshin S.V., Medvedeva M.G., Rodin S.B., Egorov E.E. Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes. United States Patent: 7,401,318, July 15, 2008. http://patft.uspto.gov/[...]
  97. Galatenko A.V., Gasanov E.E., Lyalin I.V. Method and apparatus for controlling congestion during integrated circuit design resynthesis. United States Patent: 7,401,313, July 15, 2008. http://patft.uspto.gov/[...]
  98. Galatenko A.V., Gasanov E.E., Zolotykh A.A. Method and apparatus for performing logical transformations for global routing. United States Patent: 7,398,486, July 8, 2008. http://patft.uspto.gov/[...]
  99. Panteleev P.A., Nikitin A.A., Andreev A.E. Method and system for converting netlist of integrated circuit between libraries. United States Patent: 7,380,223, May 27, 2008. http://patft.uspto.gov/[...]
  100. Nikitin A.A., Neznanov I.V., Andreev A.E. RRAM controller built in self test memory. United States Patent: 7,356,743, April 8, 2008. http://patft.uspto.gov/[...]
  101. Golubtsov I., Aleshin S.V., Scepanovic R., Rodin S.B., Medvedeva M.M., Uzhakov S.V., Egorov E.E., Strelkova N. Method and system for analyzing the quality of an OPC mask. United States Patent: 7,340,706, March 4, 2008. http://patft.uspto.gov/[...]
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